As well known in the art, a cache memory is employed to increase the performance of a data processing system when a CPU (central processing unit) requires a large bandwidth to communicate with a main memory. To effectively increase the memory bandwidth, the cache memory stores frequently used instructions and data stored at the main memory. Typically, the cache memory is constructed by a SRAM (static random access memory) to have an access time shorter than that of the main memory constructed by a DRAM (dynamic random access memory). As a result, the system performance is improved since the CPU idle time is reduced due to some of the data being read from the cache memory.
In the conventional data processing system, the cache memory is accessed by the CPU in one of two cache memory access forms: that is, a cache memory parallel-access form and a cache memory serial-access form, which will be described below.
FIG. 1 provides a block diagram of the data processing system 100 for illustrating the cache memory parallel-access form. The data processing system 100 comprises a CPU 102, a cache memory 104, a main memory 106, a DMA (direct memory access) 108 and an I/O (input/output) module 110, each being connected to a system bus 112 for communication with another block.
In the parallel-access form as shown in FIG. 1, an address for data desired by the CPU 102 is provided to the cache memory 104 and the main memory 106 via the system bus 112 simultaneously. Then, a cache memory access cycle and a main memory access cycle are initiated simultaneously. As described above, the access time for the cache memory access cycle is much shorter than the access time for the main memory access cycle.
If the desired data is stored at the cache memory 104, i.e., a cache hit occurs, the CPU 102 is provided with the desired data from the cache memory 104 and stops without completing the main memory access cycle. If not, i.e., a cache miss occurs, the CPU 102 is provided with the desired data from the main memory 106 by completing the main memory access cycle. And also, the cache memory 104 stores the data provided to the CPU 102 for further use.
In other words, the maximum access time in the parallel-access form is the access time of the main memory access cycle since the CPU 102 accesses both memories 104 and 106 simultaneously.
However, in the parallel-access form, the CPU 102 occupies the system bus 112 when the cache hit occurs as well as when the cache miss occurs. Therefore, the system bus efficiency is low since other bus masters, e.g., the DMA 108 and the I/O module 110, cannot occupy the system bus 112 whenever the CPU 102 has an access thereto. And, the CPU 102 cannot access the cache memory while another bus master occupies the system bus 112.
Referring to FIG. 2, there is provided a block diagram of a data processing system 200 for illustrating the cache memory serial-access form. The data processing system 200 comprises a cache memory 204, a main memory 206, a DMA 208 and an I/O (input/output) module 210, each being connected to a system bus 212, and the CPU 202 coupled with the cache memory 204.
In the serial-access form as shown in FIG. 2, the address for the data desired by the CPU 202 is provided to the cache memory 204 first. If the cache hit occurs, the CPU 202 is provided with the desired data without further delay.
If the cache miss occurs, the address is provided from the cache memory 204 to the main memory 206 via the system bus 212. And then, the desired data is retrieved from the main memory 206 to be stored in the cache memory 204 for further use and finally provided to the CPU 202.
Since the CPU 202 checks first the cache memory 204, the DMA 208 and the I/O module 210 can access the main memory via the system bus 212 during the cache memory access of the CPU 202.
However, in the serial-access form, the maximum access time is the sum of the access time of the cache memory access cycle and the main memory access cycle since the main memory access cycle is initiated after the cache miss occurs. In other words, the CPU idle time is increased by the time delay due to the cache miss.